HD404054 Datasheet, PDF (20/101 Pages) Hitachi Semiconductor – HMCS400-series microcomputers designed to increase program productivity with large-capacity memory

HD404054 Series/HD404094 Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.
Table 4 Interrupt Enable Flag (IE: $000, Bit 0)
IE
Interrupt Enabled/Disabled
0
Disabled
1
Enabled
External Interrupts (INT₀, INT₁): Two external interrupt signals.
External Interrupt Request Flags (IF0, IF1: $000, $001): IF0 and IF1 are set the falling of signals input
to INT₀ and INT₁ as listed in table 5.
Table 5 External Interrupt Request Flags (IF0, IF1: $000, $001)
IF0, IF1
0
1
Interrupt Request
No
Yes
External Interrupt Masks (IM0, IM1: $000, $001): Prevent (mask) interrupt requests caused by the
corresponding external interrupt request flags, as listed in table 6.
Table 6 ExternalInterrupt Masks (IM0, 1M1: $000, $001)
IM0, IM1
0
1
Interrupt Request
Enabled
Disabled (masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.
Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2)
IFTA
0
1
Interrupt Request
No
Yes
20