HD404054 Datasheet, PDF (18/101 Pages) Hitachi Semiconductor – HMCS400-series microcomputers designed to increase program productivity with large-capacity memory

HD404054 Series/HD404094 Series
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt Control Bit
INT₀
INT₁
Timer A Timer C
IE
1
1
1
1
IF0 · IM0
1
0
0
0
IF1 · IM1
*
1
0
0
IFTA · IMTA
*
*
1
0
IFTC · IMTC
*
*
*
1
IFTD · IMTD
*
*
*
*
IFS1 · IMS1
*
*
*
*
Note: * Can be either 0 or 1. Their values have no effect on operation.
Timer D
1
0
0
0
0
1
*
Serial 1
1
0
0
0
0
0
1
Instruction cycles
1
2
3
4
5
6
Instruction
execution ^*
Interrupt
acceptance
Stacking
IE reset
Vector address
generation
Execution of JMPL
instruction at vector address
Note: ^* The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Figure 9 Interrupt Processing Sequence
Execution of
instruction at
start address
of interrupt
routine
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