HN58X24512I Datasheet, PDF (8/20 Pages) Hitachi Semiconductor – Two-wire serial interface 512k EEPROM (64-kword ´ 8-bit)

HN58X24512I
Device Address (A0, A1)
Up to four devices can be addressed on the same bus by setting the levels on these pins to different
combinations. The levels on these pins are compared with the device address code which are inputted
thought the SDA pin. These device is selected if the compare is successfully done. These pins are
internally pulled down to V_SS. The device read these pins as low if unconnected.
Pin Connections for A0, A1
Pin connection
Max connect
Memory size number
A1
A0
Note
512k bit
4
V_CC/V _SS * ¹
V_CC/V_SS
Note: 1. “V_CC/V_SS” means that device address pin should be connected to V_CC or V_SS. The A1 and A0 are
read as V_SS, if left unconnected.
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in
the following table. When the WP is low, write operation for all memory arrays are allowed. The read
operation is always activated irrespective of the WP pin status. When left unconnected, the WP input is
read as V_IL because the WP pin is internally pulled down to V_SS.
Write Protect Area
WP pin status
V_IH
V_IL
Write protect area
Full (512k bit)
Normal read/write operation
8