HN58V65A Datasheet, PDF (8/27 Pages) Hitachi Semiconductor – 64 k EEPROM (8-kword x 8-bit) Ready/Busy function, RES function (HN58V66A)

HN58V65A Series, HN58V66A Series
Write Cycle 1 (V_CC = 2.7 to 4.5 V)
Parameter
Symbol Min*³ Typ Max Unit Test conditions
Address setup time
t _AS
0
—
—
ns
Address hold time
t _AH
50
—
—
ns
CE to write setup time (WE controlled)
t _CS
0
—
—
ns
CE hold time (WE controlled)
t _CH
0
—
—
ns
WE to write setup time (CE controlled)
t _WS
0
—
—
ns
WE hold time (CE controlled)
t _WH
0
—
—
ns
OE to write setup time
t _OES
0
—
—
ns
OE hold time
t _OEH
0
—
—
ns
Data setup time
t _DS
50
—
—
ns
Data hold time
t _DH
0
—
—
ns
WE pulse width (WE controlled)
t _WP
200 —
—
ns
CE pulse width (CE controlled)
t _CW
200 —
—
ns
Data latch time
t _DL
100 —
—
ns
Byte load cycle
t _BLC
0.3 —
30
µs
Byte load window
t _BL
100 —
—
µs
Write cycle time
t _WC
—
—
10*⁴ ms
Time to device busy
t _DB
120 —
—
ns
Write start time
t _DW
0*⁵
—
—
ns
Reset protect time*²
t _RP
100 —
—
µs
Reset high time*^{2, 6}
t _RES
1
—
—
µs
Notes: 1. t_DF and t_DFR are defined as the time at which the outputs achieve the open circuit conditions
and
are no longer driven.
2. This function is supported by only the HN58V66A series.
3. Use this device in longer cycle than this value.
4. t_WC must be longer than this value unless polling techniques or RDY/Busy are used. This
device automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after t_DW if polling techniques or RDY/Busy are
used.
6. This parameter is sampled and not 100% tested.
7. A6 through A12 are page addresses and these addresses are latched at the first falling edge
of WE.
8. A6 through A12 are page addresses and these addresses are latched at the first falling edge
of CE.
9. See AC read characteristics.