HD66523 Datasheet, PDF (7/19 Pages) Hitachi Semiconductor – (240-Channel Common Driver with Internal LCD Timing Circuit)

HD66523
Internal Function Description
1. Generation of Signals CL1 and FLM: Signal CL1 shifts the scanning signal of the common driver.
It is a 50% duty-ratio clock that changes level synchronously with the rising edge of oscillator clock
CR.
FLM is a clock signal that goes high once every frame. One frame consists of display lines, 240 lines
if DUTY is high and 200 lines if DUTY is low, and vertical retrace period which is set with BP4 to
BP0.
2. Auto Display-off Control: This functions prevents incorrect display after reset release. The display is
turned off four frames following after reset release. In addition, the display off control signal shown in
Figure 4 is output by pin '2&. This pin is connected to pin ',632)) of the HD66522.
CR
CL1
FLM
Vertical retrace period
240
(200)
1
2
Figure 3 Generation of Signals CL1 and FLM
RESET
FLM
DOC
1
2
3
4
5
Figure 4 Automatic Display-off Control Function
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