HD66523 Datasheet, PDF (2/19 Pages) Hitachi Semiconductor – (240-Channel Common Driver with Internal LCD Timing Circuit)

HD66523
Pin Description
Classi-
fication
Power
supply
Symbol
V_CC
GND
Pin Name
V_CC
GND
Control
signals
VLCD1,
VLCD2
V , V _{EE1 EE2}
VLCD
V_EE
VRH1, VRH2
VM1, VM2
VRL1, VRL2
M/6
DUTY
VRH
VM
VRL
Master/
Slave
Duty
I/O
Power
supply
Power
supply
Power
supply
Power
supply
—
—
—
I
I
BP4 to BP0
'2&
',632))
Blanking I
period
Display off I/O
control
Display off I
LCD
timing
SHL
5(6(7
CR, C, R
Shift left I
Reset
I
Oscillator —
TEST1, TEST0 Test
I
CL1
Clock 1
I/O
FLM
First line I/O
marker
FX1, FX0
BLANK
LCD drive X1 to X240
output
Scanning I/O
function
Blank
O
X1 to X240 O
Number
of pins Functions
2
V_CC–GND: logic power supply
2
2
Power supply for LCD driving circuit
2
2
LCD drive level power supply
2
2
1
Select master or slave mode.
1
Selects the display duty cycle.
Low level: 1/200 display duty ratio
High level:
1/240 display duty ratio
5
Set vertical retrace period
1
Control the display-off function.
1
Turn off the LCD.
During display off, all LCD driver output VM
level
1
Pin SHL switches the shift direction of the
scanning direction.
1
Reset the LSI internally.
3
Oscillator with external resistor and
capacitor
2
Test pins, must be connected to GND.
1
The bidirectional shift register shifts data at
the falling edge of CL1.
During master mode, this pin outputs a data
transfer clock with a two times larger cycle
than the internal oscillator (or the cycle of
the external clock) with a duty of 50%.
During slave mode, this pin inputs the
external data transfer clock.
1
During master mode, pin FLM outputs the
first line marker signal.
During slave mode, this pin inputs the
external data first line marker signal.
2
Output scanning function signals during
master mode. Input scanning function
signals during slave mode.
1
This pin shows vertical retrace period.
240
Select one from among three levels, VRH,
VM and VRL.
1103