HD4074344 Datasheet, PDF (65/100 Pages) Hitachi Semiconductor – 4-bit microcomputers

HD404344R Series/HD404394 Series
Output Level Control During Idle States: The output level of the SO pin can be set during either STS
wait state or transmit clock wait state by software. During idle states, the output level is controlled by
writing to bit 1 (PMRC1) of port mode register C (PMRC: $025). An example of output level control
during idle states is shown in figure 43. During transfer state, output level control cannot be executed.
State
MCU reset
PMRA write
SMR write
PMRC write
SRL, SRU
write
STS
instruction
SCK pin
(input)
SO pin
IFS
State
MCU reset
PMRA write
SMR write
PMRC write
SRL, SRU
write
STS
instruction
SCK pin
(output)
SO pin
IFS
STS wait state
Transmit clock
wait state
Transfer state
Port selection
External clock selection
Output level control in
idle states
Data write for transmission
Transmit clock
wait state
STS wait state
Dummy write for
state transition
Output level control in
idle states
Undefined
LSB
MSB
STS wait state
External clock mode
Transmit clock
wait state
Transfer state
Flag reset at transfer completion
STS wait state
Port selection
Internal clock selection
Output level control in
idle states
Data write for transmission
Output level control in
idle states
Undefined
LSB
MSB
Internal clock mode
Flag reset at transfer completion
Figure 43 Example of Serial Interface Operation Sequence
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