HD4074344 Datasheet, PDF (27/100 Pages) Hitachi Semiconductor – 4-bit microcomputers

HD404344R Series/HD404394 Series
Table 2 Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt Control Bit
INT₀
Timer B
Timer C
A/D
IE
1
1
1
1
IF0 · IM0
1
0
0
0
IFTB · IMTB
*
1
0
0
IFTC · IMTC
*
*
1
0
IFAD · IMAD
*
*
*
1
IFS · IMS
*
*
*
*
Note: * Can be either 0 or 1. Their values have no effect on operation.
Serial
1
0
0
0
0
1
Instruction cycles
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Stacking;
IE reset
Stacking;
Vector address
generation
Execution of JMPL
instruction at vector address
Execution of
instruction at
start address
of interrupt
routine
Note: * The stack is accessed and the interrupt enable flag is reset after the instruction is executed, even
if it is a two-cycle instruction.
Figure 9 Interrupt Processing Sequence
27