HD4074344 Datasheet, PDF (56/100 Pages) Hitachi Semiconductor – 4-bit microcomputers

HD404344R Series/HD404394 Series
Watchdog on
flag (WDON)
Watchdog timer
controller
System reset signal
Interrupt request
flag of timer C
(IFTC)
TOC
System ^øPER
clock
Timer read register CU (TRCU)
Timer output
controller
Clock
Timer
output
control
Timer read
register C lower
(TRCL)
Timer counter C
(TCC)
Overflow
Timer write
register C upper
(TWCU)
Selector
Prescaler S (PSS)
Free-running/
reload timer
control
3
Timer write
register C lower
(TWCL)
Timer mode
register C (TMC)
Port mode
register A (PMRA)
Figure 33 Timer C Block Diagram
Timer C Operation
• Free-running/reload timer operation: The selection of the free-running/reload timer, input clock source,
and prescaler division ratio is done by timer mode register C (TMC: $00D).
Timer C is initialized to the data, which is written to timer write register C (TWCL: $00E, TWCU:
$00F) by software. The data is then incremented in steps of 1 by using the input clock. If the clock input
is continued after timer C is set to $FF, an overflow occurs. Timer C then begins counting again, setting
the timer to the value in timer write register C (TWCL: $00E, TWCU: $00F) when the reload timer is
selected, or reset to $00 when the free-running timer is selected.
The timer C interrupt request flag is set by an overflow. Resetting the timer C interrupt request flag
(IFTC: $002, bit 2) is executed by either software or by an MCU reset.
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