HN58S65A Datasheet, PDF (6/18 Pages) Hitachi Semiconductor – 64 k EEPROM (8-kword x 8-bit) Ready/Busy function

HN58S65A Series
Write Cycle
Parameter
Symbol Min*² Typ
Test
Max
Unit conditions
Address setup time
t _AS
0
—
—
ns
Address hold time
t _AH
150
—
—
ns
CE to write setup time (WE controlled) t_CS
0
—
—
ns
CE hold time (WE controlled)
t _CH
0
—
—
ns
WE to write setup time (CE controlled) t_WS
0
—
—
ns
WE hold time (CE controlled)
t _WH
0
—
—
ns
OE to write setup time
t _OES
0
—
—
ns
OE hold time
t _OEH
0
—
—
ns
Data setup time
t _DS
150
—
—
ns
Data hold time
t _DH
0
—
—
ns
WE pulse width (WE controlled)
t _WP
200
—
—
ns
CE pulse width (CE controlled)
t _CW
200
—
—
ns
Data latch time
t _DL
200
—
—
ns
Byte load cycle
t _BLC
0.4
—
30
µs
Byte load window
t _BL
100
—
—
µs
Write cycle time
t _WC
—
—
15*³
ms
Time to device busy
t _DB
120
—
—
ns
Write start time
t _DW
0*⁴
—
—
ns
Notes: 1. t_DF is defined as the time at which the outputs achieve the open circuit conditions and are no
longer driven.
2. Use this device in longer cycle than this value.
3. t_WC must be longer than this value unless polling techniques or RDY/Busy are used. This
device automatically completes the internal write operation within this value.
4. Next read or write operation can be initiated after t_DW if polling techniques or RDY/Busy are
used.
5. A6 through A12 are page addresses and these addresses are latched at the first falling edge
of WE.
6. A6 through A12 are page addresses and these addresses are latched at the first falling edge
of CE.
7. See AC read characteristics.