HD74AC112 Datasheet, PDF (5/10 Pages) Hitachi Semiconductor – Dual JK Negative Edge-Triggered Flip-Flop

HD74AC112/HD74ACT112
AC Characteristics: HD74ACT112
Item
Maximum clock
frequency
Symbol V_CC (V)*¹
f _max
5.0
Ta = +25°C
C_L = 50 pF
Min Typ
100 —
Propagation delay
t _PLH
5.0
1.0
C_P to Q or Q
Propagation delay
t _PHL
5.0
1.0
C_P to Q or Q
Propagation delay
t _PLH
5.0
1.0
C_D, S_D to Q or Q
Propagation delay
t _PHL
5.0
1.0
C_D, S_D to Q or Q
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
10.5
10.5
8.0
10.5
Max
—
13.0
13.0
10.0
12.5
Ta = –40°C to +85°C
C_L = 50 pF
Min
Max
80
—
Unit
MHz
1.0
14.0
ns
1.0
14.0
1.0
11.0
1.0
13.5
AC Operating Requirements: HD74ACT112
Ta = +25°C
C_L = 50 pF
Item
Symbol V_CC (V)*¹ Typ
Setup time
J or K to C_P
t _su
5.0
2.5
Hold time
C_P to J or K
t_h
5.0
0.0
Pulse width
C_P or C_D or S_D
t_w
5.0
4.5
Recovery time
C_D , S_D to C_P
t _rec
5.0
–2.5
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Ta = –40°C
to +85°C
C_L = 50 pF
Guaranteed Minimum
7.0
8.0
1.5
1.5
7.0
8.0
3.0
3.0
Unit
ns
Capacitance
Item
Input capacitance
Power dissipation capacitance
Symbol
C_IN
C_PD
Typ
4.5
35.0
Unit
pF
pF
Condition
V_CC = 5.5 V
V_CC = 5.0 V
5