HD74AC112 Datasheet, PDF (4/10 Pages) Hitachi Semiconductor – Dual JK Negative Edge-Triggered Flip-Flop

HD74AC112/HD74ACT112
AC Characteristics: HD74AC112
Item
Maximum clock
frequency
Symbol
f _max
V_CC (V)*¹
3.3
5.0
Ta = +25°C
C_L = 50 pF
Min Typ
125 —
150 —
Propagation delay
t _PLH
3.3
1.0
C_P to Q or Q
5.0
1.0
Propagation delay
t _PHL
3.3
1.0
C_P to Q or Q
5.0
1.0
Propagation delay
t _PLH
3.3
1.0
C_D, S_D to Q or Q
5.0
1.0
Propagation delay
t _PHL
3.3
1.0
C_D, S_D to Q or Q
5.0
1.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
11.0
8.5
11.0
8.5
9.5
7.0
11.5
9.0
Max
—
—
14.0
11.0
14.0
11.0
12.5
9.5
14.5
11.0
Ta = –40°C to +85°C
C_L = 50 pF
Min
Max
100
—
125
—
1.0
15.0
1.0
12.0
1.0
15.0
1.0
12.0
1.0
13.5
1.0
10.5
1.0
15.5
1.0
12.5
Unit
MHz
ns
AC Operating Requirements: HD74AC112
Ta = +25°C
C_L = 50 pF
Item
Symbol V_CC (V)*¹ Typ
Setup time
t _su
3.3
3.0
J or K to C_P
5.0
2.0
Hold time
t_h
3.3
–1.5
C_P to J or K
5.0
–0.5
Pulse width
t_w
3.3
2.0
C_P or C_D or S_D
5.0
2.0
Recovery time
t _rec
3.3
–1.0
C_D or S_D to C_P
5.0
–1.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Ta = –40°C
to +85°C
C_L = 50 pF
Guaranteed Minimum
5.5
6.0
4.5
4.6
0.0
0.0
0.0
0.0
5.5
7.0
4.5
5.0
3.5
3.5
3.0
3.0
Unit
ns
4