HD74AC112 Datasheet, PDF (3/10 Pages) Hitachi Semiconductor – Dual JK Negative Edge-Triggered Flip-Flop

Truth Table
Inputs
@t_n
J
K
L
L
L
H
H
L
H
H
t_n :
t_{n + 1} :
H:
L:
Bit time before clock pulse.
Bit time after clock pulse.
High Voltage Level
Low Voltage Level
HD74AC112/HD74ACT112
Outputs
@t_{n + 1}
Q
Qn
L
H
Qn
Logic Diagram
S_D
Q
C_D
J
CP
#CP
Q
K
# _CP
CP
CP
CP
#
CP
#
CP
CP
CP
#
CP
DC Characteristics (unless otherwise specified)
Item
Symbol Max
Unit
Maximum quiescent supply current I_CC
80
µA
Maximum quiescent supply current I_CC
8.0
µA
Maximum additional I_CC/input
(HD74ACT112)
I _CCT
1.5
mA
Condition
V_IN = V_CC or ground, V_CC = 5.5 V,
Ta = Worst case
V_IN = V_CC or ground, V_CC = 5.5 V,
Ta = 25°C
V_IN = V_CC – 2.1 V, V_CC = 5.5 V
Ta = Worst case
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