HD74AC112 Datasheet, PDF (1/10 Pages) Hitachi Semiconductor – Dual JK Negative Edge-Triggered Flip-Flop

HD74AC112/HD74ACT112
Dual JK Negative Edge-Triggered Flip-Flop
Description
The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to
each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level
of the J and K inputs may change when the clock is High and the bistable will perform according to the
Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs
on the falling edge of the clock pulse.
Features
• Outputs Source/Sink 24 mA
• HD74ACT112 has TTL-Compatible Inputs
Pin Arrangement
CP₁ 1
K₁ 2
J₁ 3
S_D1 4
Q₁ 5
Q₁ 6
Q₂ 7
GND 8
(Top view)
16 V_CC
15 C_D1
14 C_D2
13 CP₂
12 K₂
11 J₂
10 S_D2
9 Q₂