R1LP0408C Datasheet, PDF (12/14 Pages) Hitachi Semiconductor – Wide Temperature Range Version 4 M SRAM (512-kword × 8-bit)

R1LP0408C-I Series
Low V_CC Data Retention Characteristics
(Ta = −40 to +85°C)
Parameter
Symbol Min Typ*⁴ Max Unit Test conditions*³
V_CC for data retention
Data retention
to +85°C
current
to +40°C
−20°C to +25°C
V_DR
I_CCDR*¹
I_CCDR*²
I_CCDR*¹
I_CCDR*²
I_CCDR*¹
I_CCDR*²
2


 V CS# ≥ V_CC − 0.2 V, Vin ≥ 0 V
20 µA V_CC = 3.0 V, Vin ≥ 0 V
CS# ≥ V_CC − 0.2 V
10
 1.0 10 µA
 1.0 3
 0.8 10 µA
 0.8 3
Chip deselect to data retention time
t_CDR
Operation recovery time
t_R
0   ns See retention waveform
t_RC*⁵   ns
Notes: 1. This characteristic is guaranteed only for L version.
2. This characteristic is guaranteed only for SL version.
3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode,
Vin levels (address, WE#, OE#, I/O) can be in the high impedance state.
4. Typical values are at V_CC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
5. t_RC = read cycle time.
Low V_CC Data Retention Timing Waveform (CS# Controlled)
t_CDR
Data retention mode
t_R
V_CC
4.5 V
2.4 V
V_DR
CS#
0V
CS# ≥ V_CC – 0.2 V
Rev.1.00, Aug.01.2003, page 12 of 13