HD74LV165A Datasheet, PDF (1/17 Pages) Hitachi Semiconductor – Parallel-Load 8-bit Shift Register

HD74LV165A
Parallel-Load 8-bit Shift Register
ADE-205-267 (Z)
1st Edition
March 1999
Description
The HD74LV165A is 8-bit serial shift register shifts data from Q_A to Q_H when clocked. Parallel inputs to
each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a
complementary output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit
function. Holding either of the clock inputs high inhibits clocking, and high enables the other clock input.
Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the
Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the register
independent of the state of the clock.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
• V_CC = 2.0 V to 5.5 V operation
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• All outputs V_O (Max.) = 5.5 V (@V_CC = 0 V)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.3 V (@V_CC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@V_CC = 3.0 V to 3.6 V), ±12 mA (@V_CC = 4.5 V to 5.5 V)