82C37 Datasheet, PDF (15/23 Pages) Harris Corporation – CMOS High Performance Programmable DMA Controller

82C37A
AC Electrical Specifications
V_CC = +5.0V ±10%, GND = 0V, T_A = 0^oC to +70^oC (C82C37A),
T_A = -40^oC to +85^oC (I82C37A),
T_A = -55^oC to +125^oC (M82C37A)
82C37A-5
82C37A
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
DMA (MASTER) MODE
82C37A-12
MIN
MAX
(1)TAEL
AEN HIGH from CLK LOW (S1) Delay
-
175
-
105
-
50
Time
(2)TAET
AEN LOW from CLK HIGH (SI) Delay
-
130
-
80
-
50
Time
(3)TAFAB
ADR Active to Float Delay from CLK
-
90
-
55
-
55
HIGH
(4)TAFC
READ or WRITE Float Delay from
CLK HIGH
-
120
-
75
-
50
(5)TAFDB
DB Active to Float Delay from CLK
HIGH
-
170
-
135
-
90
(6)TAHR
ADR from READ HIGH Hold Time
TCY-100
-
TCY-75
-
TCY-65
-
(7)TAHS
DB from ADSTB LOW Hold Time
TCL-18
-
TCL-18
-
TCL-18
-
(8)TAHW
ADR from WRITE HIGH Hold Time
TCY-65
-
TCY-65
-
TCY-50
-
(9)TAK
DACK Valid from CLK LOW
Delay Time
-
170
-
105
-
69
EOP HIGH from CLK HIGH
Delay Time
-
170
-
105
-
90
EOP LOW from CLK HIGH
Delay Time
-
100
-
60
-
35
(10)TASM
ADR Stable from CLK HIGH
-
110
-
60
-
50
(11)TASS
DB to ADSTB LOW Setup Time
TCH-20
-
TCH-20
-
TCH-20
-
(12)TCH
CLK HIGH Time (Transitions 10ns)
70
-
55
-
30
-
(13)TCL
CLK LOW Time (Transitions 10ns)
50
-
43
-
30
-
(14)TCY
CLK Cycle Time
200
-
125
-
80
-
(15)TDCL
CLK HIGH to READ or WRITE LOW
-
190
-
130
-
120
Delay
(16)TDCTR
READ HIGH from CLK HIGH (S4)
Delay Time
-
190
-
115
-
80
(17)TDCTW WRITE HIGH from CLK HIGH (S4)
-
130
-
80
-
70
Delay Time
(18)TDQ
HRQ Valid from CLK HIGH
Delay Time
-
120
-
75
-
30
(19)TEPH
EOP Hold Time from CLK LOW (S2)
90
-
90
-
50
-
(20)TEPS
EOP LOW to CLK LOW Setup Time
40
-
25
-
0
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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