82C37 Datasheet, PDF (12/23 Pages) Harris Corporation – CMOS High Performance Programmable DMA Controller

82C37A
Application Information
Figure 6 shows an application for a DMA system utilizing the
82C37A DMA controller and the 80C88 Microprocessor. In
this application, the 82C37A DMA controller is used to
improve system performance by allowing an I/O device to
transfer data directly to or from system memory.
Components
The system clock is generated by the 82C84A clock driver
and is inverted to meet the clock high and low times required
by the 82C37A DMA controller. The four OR gates are used
to support the 80C88 Microprocessor in minimum mode by
producing the control signals used by the processor to
access memory or I/O. A decoder is used to generate chip
select for the DMA controller and memory. The most signifi-
cant bits of the address are output on the address/data bus.
Therefore, the 82C82 octal latch is used to demultiplex the
address. Hold Acknowledge (HLDA) and Address Enable
(AEN) are “ORed” together to insure that the DMA controller
does not have bus contention with the microprocessor.
Operation
A DMA request (DREQ) is generated by the I/O device. After
receiving the DMA request, the DMA controller will issue a
Hold request (HRQ) to the processor. The system busses
are not released to the DMA controller until a Hold Acknowl-
edge signal is returned to the DMA controller from the
80C88 processor. After the Hold Acknowledge has been
received, addresses and control signals are generated by
the DMA controller to accomplish the DMA transfers. Data is
transferred directly from the I/O device to memory (or vice
versa) with IOR and MEMW (or MEMR and IOW) being
active. Note that data is not read into or driven out of the
DMA controller in I/O-to-memory or memory-to-I/O data
transfers.
82C84A
OR
82C85
CLK
HLDA
HLDA
HRQ
AX
ALE
AD0
M/IO
RD
WR
AD7
MN/MX
V_CC
80C88
MEMR
MEMCS
DECODER
ADDRESS BUS
STB
OE
OE
82C82
V_CC
47kΩ
DATA BUS
STB
82C82
ADDRESS BUS
MEMW
IOR
MEMCS
IOW MEMR
MEMW
MEMORY
DATA BUS
NOTE: The address lines need pull-up resistors.
FIGURE 6. APPLICATION FOR DMA SYSTEM
V_CC
82C37A
CLK
EOP
CS
HLDA
ADSTB _IOR
AEN
IOW
MEMR
MEMW
A0-7
HRQ
DB0-7 DREQ0
DACK
CS
DREQ
I/O
DEVICE
IOR
IOW
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