82C37 Datasheet, PDF (11/23 Pages) Harris Corporation – CMOS High Performance Programmable DMA Controller

82C37A
Software Commands
There are special software commands which can be
executed by reading or writing to the 82C37A. These com-
mands do not depend on the specific data pattern on the
data bus, but are activated by the I/O operation itself. On
read type commands, the data value is not guaranteed.
These commands are:
Clear First/Last Flip-Flop - This command is executed
prior to writing or reading new address or word count infor-
mation to the 82C37A. This command initializes the flip-flop
to a known state (low byte first) so that subsequent accesses
to register contents by the microprocessor will address
upper and lower bytes in the correct sequence.
Set First/Last Flip-Flop - This command will set the flip-flop
to select the high byte first on read and write operations to
address and word count registers.
Master Clear - This software instruction has the same effect
as the hardware Reset. The Command, Status, Request,
and Temporary registers, and Internal First/Last Flip-Flop
and mode register counter are cleared and the Mask register
is set. The 82C37A will enter the idle cycle.
Clear Mask Register - This command clears the mask bits
of all four channels, enabling them to accept DMA requests.
Clear Mode Register Counter - Since only one address
location is available for reading the Mode registers, an inter-
nal two-bit counter has been included to select Mode regis-
ters during read operation. To read the Mode registers, first
execute the Clear Mode Register Counter command, then
do consecutive reads until the desired channel is read. Read
order is channel 0 first, channel 3 last. The lower two bits on
all Mode registers will read as ones.
External EOP Operation
The EOP pin is a bidirectional, open drain pin which may be
driven by external signals to terminate DMA operation.
Because EOP is an open drain pin an external pull-up resis-
tor to V_CC is required. The value of the external pull-up
resistor used should guarantee a rise time of less than
125ns. It is important to note that the 82C37A will not accept
external EOP signals when it is in a SI (Idle) state. The
controller must be active to latch EXT EOP. Once latched,
the EXT EOP will be acted upon during the next S2 state,
unless the 82C37A enters an idle state first. In the latter
case, the latched EOP is cleared. External EOP pulses
occurring between active DMA transfers in demand mode
will not be recognized, since the 82C37A is in an SI state.
CHANNEL
REGISTER
0
Base and Current Address
Current Address
Base and Current Word
Count
Current Word Count
1
Base and Current Address
Current Address
Base and Current Word
Count
Current Word Count
2
Base and Current Address
Current Address
Base and Current Word
Count
Current Word Count
3
Base and Current Address
Current Address
Base and Current Word
Count
Current Word Count
SIGNALS
FIRST/LAST
FLIP-FLOP
OPERATION CS IOR IOW A3 A2 A1 A0
STATE
Write
0100000
0
0100000
1
Read
0010000
0
0010000
1
Write
0100001
0
0100001
1
Read
0010001
0
0010001
1
Write
0100010
0
0100010
1
Read
0010010
0
0010010
1
Write
0100011
0
0100011
1
Read
0010011
0
0010011
1
Write
0100100
0
0100100
1
Read
0010100
0
0010100
1
Write
0100101
0
0100101
1
Read
0010101
0
0010101
1
Write
Read
Write
Read
0100110
0
0100110
1
00101100
00101101
01001110
01001111
00101110
00101111
FIGURE 5. WORD COUNT AND ADDRESS REGISTER COMMAND CODES
DATA
BUS
DB0-DB7
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
4-202