82C37 Datasheet, PDF (10/23 Pages) Harris Corporation – CMOS High Performance Programmable DMA Controller

82C37A
Mask Register - Each channel has associated with it a mask
bit which can be set to disable an incoming DREQ. Each
mask bit is set when its associated channel produces an EOP
if the channel is not programmed to Autoinitialize. Each bit of
the 4-bit Mask register may also be set or cleared separately
or simultaneously under software control. The entire register
is also set by a Reset or Master clear. This disables all hard-
ware DMA requests until a Clear Mask Register instruction
allows them to occur. The instruction to separately set or clear
the mask bits is similar in form to that used with the Request
register. Refer to the following diagram and Figure 4 for
details. When reading the Mask register, bits 4-7 will always
read as logical ones, and bits 0-3 will display the mask bits of
channels 0-3, respectively. The 4 bits of the Mask register
may be cleared simultaneously by using the Clear Mask Reg-
ister command (see software commands section).
Mask Register
76543210
BIT NUMBER
Don’t Care
00 Select Channel 0 mask bit
01 Select Channel 1 mask bit
10 Select Channel 2 mask bit
11 Select Channel 3 mask bit
Status Register - The Status register is available to be read
out of the 82C37A by the microprocessor. It contains
information about the status of the devices at this point. This
information includes which channels have reached a terminal
count and which channels have pending DMA requests. Bits
0-3 are set every time a TC is reached by that channel or an
external EOP is applied. These bits are cleared upon RESET,
Master Clear, and on each Status Read. Bits 4-7 are set
whenever their corresponding channel is requesting service,
regardless of the mask bit state. If the mask bits are set, soft-
ware can poll the Status register to determine which channels
have DREQs, and selectively clear a mask bit, thus allowing
user defined service priority. Status bits 4-7 are updated while
the clock is high, and latched on the falling edge. Status Bits
4-7 are cleared upon RESET or Master Clear.
Status Register
76543210
BIT NUMBER
1 Channel 0 has reached TC
1 Channel 1 has reached TC
1 Channel 2 has reached TC
0 Clear mask bit
1 Set mask bit
All four bits of the Mask register may also be written with a
single command.
1 Channel 3 has reached TC
1 Channel 0 request
1 Channel 1 request
76543210
BIT NUMBER
1 Channel 2 request
Don’t Care,
Write
All Ones,
Read
0 Clear Channel 0 mask bit
1 Set Channel 0 mask bit
0 Clear Channel 1 mask bit
1 Set Channel 1 mask bit
0 Clear Channel 2 mask bit
1 Set Channel 2 mask bit
0 Clear Channel 3 mask bit
1 Set Channel 3 mask bit
1 Channel 3 request
Temporary Register - The Temporary register is used to
hold data during memory-to-memory transfers. Following the
completion of the transfers, the last byte moved can be read
by the microprocessor. The Temporary register always
contains the last byte transferred in the previous memory-to-
memory operation, unless cleared by a Reset or Master
Clear.
OPERATION
A3
A2
A1
A0
IOR
IOW
Read Status Register
Write Command Register
Read Request Register
Write Request Register
Read Command Register
Write Single Mask Bit
Read Mode Register
Write Mode Register
Set First/Last F/F
Clear First/Last F/F
Read Temporary Register
Master Clear
Clear Mode Reg. Counter
Clear Mask Register
Read All Mask Bits
Write All Mask Bits
1
0
0
0
0
1
1
0
0
0
1
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
0
0
1
1
1
0
0
1
0
1
1
0
1
0
1
1
1
0
1
1
0
1
1
1
0
0
1
1
1
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
0
FIGURE 4. SOFTWARE COMMAND CODES AND REGISTER CODES
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