HMN1288DV Datasheet, PDF (8/9 Pages) Hanbit Electronics Co.,Ltd – Non-Volatile SRAM Module 1Mbit (128K x 8-Bit), 32Pin-DIP, 3.3V

HANBit
- WRITE CYCLE NO.2 (/CE-Controlled)^*1,2,3,4,5
Address
tAS
/CE
tWC
tAW
tCW
tWP
/WE
tDW
DIN
Data-in
tWZ
DOUT
Data Undefined
HMN1288DV
tWR2
tDH2
High-Z
NOTE:
1. /CE or /WE must be high during address transition.
2. Because I/O may be active (/OE low) during this period, data input signals of opposite
polarity to the outputs must not be applied.
3. If /OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either t DH1 or tDH2 must be met.
- POWER-DOWN/POWER-UP TIMING
tPF
VCC
4.75
VPFD
VPFD
4.25
VSO
VSO
tFS
tWPT
tDR
tPU
tCER
/CE
URL : www.hbe.co.kr
8
Rev. 1.0 (June, 2004)
FinePrint pdfFactory 평 가 판 으 로 만 든 PDFhttp://www.softvision.co.kr
HANBit Electronics Co.,Ltd