HMN4M8D Datasheet, PDF (6/9 Pages) Hanbit Electronics Co.,Ltd – Non-Volatile SRAM MODULE 32Mbit (4,096K x 8-Bit), 40Pin-DIP, 5V

HANBit
HMN4M8D
DATA RETENTION CHARACTERISTICS (T_A= T_OPR, V_CC=5V)
PARAMETER
SYMBOL
CONDITIONS
MIN
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
V_DR
CE≥Vcc-0.2V
2.0
I_DR
Vcc=3.0V, CE≥Vcc
t_SDR
See data retention waveform
0
t_RDR
5
POWER-DOWN/POWER-UP CYCLE (T_A= T_OPR, V_CC=5V)
PARAMETER
SYMBOL
CONDITIONS
MIN
V_CC slew, 4.75 to 4.25V
t_PF
300
V_CC slew, 4.75 to V_SO
t_FS
10
V_CC slew, V_SO to V_PFD (max)
t_PU
0
Chip enable recovery time
Time during which SRAM
t_CER
is write-protected after V_CC
passes V_PFD on power-up.
40
Data-retention time in
Absence of V_CC
t_DR
T_A = 25℃
5
Write-protect time
Delay after Vcc slews down
t_WPT
past V_PFD before SRAM is
Write-protected.
40
TYP.
-
-
-
-
MAX
5.5
20
-
-
UNIT
V
uA
ms
TYP.
-
-
-
MAX
-
-
-
UNIT
㎲
㎲
㎲
80
120
ms
-
-
years
100
150
㎲
TIMING WAVEFORM
- Read Cycle No.1 (Address Access)*^1,2
Address
DOUT
tRC
tACC
tOH
Previous Data Valid
Data Valid
URL : www.hbe.co.kr
Rev. 1.0 (May, 2002)
6
HANBit Electronics Co.,Ltd