S11106-10_15 Datasheet, PDF (6/12 Pages) Hamamatsu Corporation – CMOS linear image sensors

CMOS linear image sensors
S11106-10, S11107-10
Timing chart
1/f(CLK)
1 2 3 4 14 15 16 17 18 19 20 21 ^Trig
CLK
Integration time
ST
thp(ST)
128 (S11106-10)
64 (S11107-10)
Video
19 clocks
tlp(ST)
tpi(ST)
1
EOS
128 (S11106-10)
64 (S11107-10)
tf(CLK)
tr(CLK)
CLK
CLK
1/f(CLK)
ST
tr(ST)
tf(ST)
thp(ST)
tpi(ST)
tlp(ST)
Video
tvd2
tvd1
KMPDC0515EB
Parameter
Symbol
S11106-10
S11107-10
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Start pulse interval
tpi(ST)
36/f(CLK)
-
-
36/f(CLK)
-
-
s
Start pulse high period
thp(ST)
4/f(CLK)
-
-
4/f(CLK)
-
-
s
Start pulse low period
tlp(ST)
32/f(CLK)
-
-
32/f(CLK)
-
-
s
Start pulse rise and fall times
tr(ST), tf(ST)
0
10
15
0
10
15
ns
Clock pulse duty ratio
-
45
50
55
45
50
55
%
Clock pulse rise and fall times
tr(CLK), tf(CLK) 0
10
15
0
10
15
ns
Video
delay
time
1*¹²
Vdd=3
Vdd=5
V
V
tvd1
-
60
-
-
35
-
-
60
-
-
35
-
ns
Video
delay
time
2*¹²
Vdd=3
Vdd=5
V
V
tvd2
-
35
-
-
30
-
-
35
-
-
30
-
ns
*12: Ta=25 °C, CLK=10 MHz, V(CLK)=V(ST)=Vdd
Note: Dark output increases if the start pulse period or the start pulse high period is lengthened.
The internal timing generator starts operation at the rising edge of CLK immediately after ST goes low. The rising edge of this
CLK is regarded as “1”.
The integration time equals the high period of ST plus 14 CLK cycles and minus 100 ns.
When the ST pulse is set to low while the shift register is operating, the operation of the shift register is reset and the next shift
register operation will start.
The integration time can be changed by changing the ratio of the high and low periods of ST.
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