S11850-1106_15 Datasheet, PDF (2/10 Pages) Hamamatsu Corporation – CCD image sensors

CCD image sensors
S11850-1106, S11851-1106
Structure
Parameter
Image size (H × V)
Pixel size (H × V)
Number of total pixels
Numbe of effective pixels
Vertical clock phase
Horizontal clock phase
Output circuit
Package
Window
*1: Hermetic sealing
S11850-1106
S11851-1106
28.672 × 0.896 mm
14 × 14 μm
2068 × 70
2048 × 64
2-phase
4-phase
One-stage MOSFET source follower
Two-stage MOSFET source follower
28-pin ceramic DIP (refer to dimensional outline)
Quartz glass*¹
Absolute maximum ratings (Ta=25 °C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Operating temperature*²
Topr
-50
-
+50
°C
Storage temperature
Tstg
-50
-
+70
°C
Output transistor drain voltage
S11850-1106
S11851-1106
VOD
-0.5
-0.5
-
-
+30
+25
V
Reset drain voltage
VRD
-0.5
-
+18
V
Output amplifier return voltage
Vret
-0.5
-
+18
V
Overflow drain voltage
VOFD
-0.5
-
+18
V
Vertical input source voltage
VISV
-0.5
-
+18
V
Horizontal input source voltage
VISH
-0.5
-
+18
V
Overflow gate voltage
VOFG
-10
-
+15
V
Vertical input gate voltage
VIG1V, VIG2V
-10
-
+15
V
Horizontal input gate voltage
VIG1H, VIG2H
-10
-
+15
V
Summing gate voltage
VSG
-10
-
+15
V
Output gate voltage
VOG
-10
-
+15
V
Reset gate voltage
VRG
-10
-
+15
V
Transfer gate voltage
VTG
-10
-
+15
V
Vertical shift register clock voltage
VP1V, VP2V
-10
-
+15
V
Horizontal shift register clock voltage
VP1H, VP2H
VP3H, VP4H
-10
-
+15
V
*2: Chip temperature
Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the
product within the absolute maximum ratings.
Operating conditions (MPP mode, Ta=25 °C)
Parameter
Symbol
S11850-1106
Min. Typ. Max.
S11851-1106
Min. Typ. Max.
Unit
Output transistor drain voltage
VOD
23
24
25
12
15
18
V
Reset drain voltage
VRD
11
12
13
14
15
16
V
Output amplifier return voltage*³
Vret
-
1
2
V
Overflow drain voltage
VOFD
11
12
13
11
12
13
V
Input source
VISV, VISH
-
VRD
-
-
VRD
-
V
Test point
Vertical input gate
VIG1V, VIG2V
-9
-8
-
-9
-8
-
V
Horizontal input gate
VIG1H, VIG2H
-9
-8
-
-9
-8
-
V
Overflow gate voltage
VOFG
0
12
13
0
13
14
V
Summing gate voltage
High
Low
VSGH
VSGL
4
6
8
4
6
8
-6
-5
-4
-6
-5
-4
V
Output gate voltage
VOG
4
5
6
4
5
6
V
Reset gate voltage
High
Low
VRGH
VRGL
4
6
8
4
6
8
-6
-5
-4
-6
-5
-4
V
Transfer gate voltage
High
Low
VTGH
VTGL
4
6
8
4
6
8
-9
-8
-7
-9
-8
-7
V
Vertical shift register clock voltage
High
VP1VH, VP2VH
4
6
8
4
6
8
Low
VP1VL, VP2VL
-9
-8
-7
-9
-8
-7
V
Horizontal shift register clock voltage
High
Low
VP1HH, VP2HH
VP3HH, VP4HH
4
VP1HL, VP2HL
VP3HL, VP4HL
-6
6
-5
8
-4
4
-6
6
-5
8
-4
V
Substrate voltage
VSS
-
0
-
-
0
-
V
External load resistance
RL
90
100 110
2.0
2.2
2.4
kΩ
*3: Output amplifier return voltage is a positive voltage with respect to Substrate voltage, but the current flows in the direction of flow
out of the sensor.
2