GS72116ATP Datasheet, PDF (9/18 Pages) GSI Technology – 128K x 16 2Mb Asynchronous SRAM

Write Cycle 1: WE control
Address
OE
CE
UB, LB
WE
Data In
Data Out
Write Cycle 2: CE control
Address
OE
CE
UB, LB
WE
Data In
Data Out
GS72116ATP/J/T/U
tWC
tAW
tWR
tCW
tBW
tAS
tWP
tWHZ
tDW tDH
Data valid
tWLZ
High impedance
tWC
tAW
tWR1
tAS
tCW
tBW
tWP
tDW tDH
Data valid
High impedance
Rev: 1.04a 10/2002
9/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.