GS72116ATP Datasheet, PDF (1/18 Pages) GSI Technology – 128K x 16 2Mb Asynchronous SRAM

GS72116ATP/J/T/U
SOJ, TSOP, FP-BGA, TQFP
128K x 16
Commercial Temp
Industrial Temp
2Mb Asynchronous SRAM
7, 8, 10, 12 ns
3.3 V V_DD
Center V_DD and V_SS
Features
• Fast access time: 7, 8, 10, 12 ns
SOJ 128K x 16-Pin Configuration
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
T: 10 mm x 10 mm, 44-pin TQFP
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
Description
A4
1
A3
2
A2
3
A1
4
A0
5
Top view
CE
6
DQ1
7
DQ2
8
DQ3
9
DQ4
10
V_DD
11
44-pin
V_SS
12
SOJ
DQ5
13
DQ6
14
DQ7
15
44
A5
43
A6
42
A7
41
OE
40
UB
39
LB
38
DQ16
37
DQ15
36
DQ14
35
DQ13
34
V_SS
33
V_DD
32
DQ12
31
DQ11
30
DQ10
The GS72116A is a high speed CMOS Static RAM organized
as 131,072 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a sin-
gle 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS72116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, a 10 mm x 10 mm TQFP package, as
well as in 400 mil SOJ and 400 mil TSOP Type-II packages.
DQ8
16
WE
17
A15
18
A14
19
A13
20
A12
21
A16
22
29
DQ9
28
NC
27
A8
26
A9
25
A10
24
A11
23
NC
Package J
Pin Descriptions
Symbol
A0–A16
DQ1–DQ16
CE
LB
UB
WE
OE
V_DD
V_SS
NC
Description
Address input
Data input/output
Chip enable input
Lower byte enable input
(DQ1 to DQ8)
Upper byte enable input
(DQ9 to DQ16)
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
Rev: 1.04a 10/2002
1/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.