GS8150V18AB Datasheet, PDF (8/25 Pages) GSI Technology – 1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM

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GS8150V18/36AB-357/333/300/250
HSTL I/O DC Input Characteristics
Parameter
Symbol
Min
Typ
Max
DC Input Logic High
V_IH (dc)
V_REF + 100
—
V_DDQ + 300
DC Input Logic Low
V_IL (dc)
–300
—
V_REF – 100
DC Clock Input Differential Voltage
V_DIF (dc)
100
—
V_DDQ + 300
V_REF DC Voltage
V_REF (dc) V_DDQ /2 – 0.1
—
V_DDQ /2 + 0.1
Clock Input Voltag
V_CK (dc)
–300
—
V_DDQ + 300
Clock Input Commone Mode Voltage
V_CM (dc)
600
750
900
Notes:
1. The peak to peak AC component superimposed on V_REF may not exceed 5% of the DC component of V_REF.
2. SRAM performance is a function of clock input differential voltage (V_DIF).
3. To guarantee AC characteristics, V_IH,V_IL,Trise and Tfall of inputs and clocks must be within 10% of each other.
4. For devices supplied with HSTL I/O input buffers.Compatible with both 1.8 V and 1.5 V I/O drivers.
5. See AC Input Definition drawing below.
Units
mV
mV
mV
V
V
V
Notes
2
1
HSTL I/O AC Input Characteristics
Parameter
Symbol
Min
Max
Units Notes
AC Input Logic High
V_IH (ac)
V_REF + 200
—
mV
3,4
AC Input Logic Low
AC Clock Input Differential Voltage
V_IL (ac)
V_DIF (ac)
—
V_REF – 200
mV
3,4
800
—
mV
2,3
V_REF Peak to Peak AC Voltage
V_REF (ac)
—
5% V_REF (DC)
mV
1
Notes:
1. The peak to peak AC component superimposed on V_REF may not exceed 5% of the DC component of V_REF.
2. SRAM performance is a function of clock input differential voltage (V_DIF). The RAM can be operated with a single ended clocking with
either CK or CK tied to V_REF.
3. To guarantee AC characteristics, V_IH,V_IL,Trise and Tfall of inputs and clocks must be within 10% of each other.
4. For devices supplied with HSTL I/O input buffers.Compatible with both 1.8 V and 1.5 V I/O drivers.
5. See AC Input Definition drawing below.
Rev: 1.04 4/2005
8/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology