GS8150V18AB Datasheet, PDF (16/25 Pages) GSI Technology – 1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM

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GS8150V18/36AB-357/333/300/250
JTAG TAP Block Diagram
····· ···
Boundary Scan Register
·
·
·
0
Bypass Register
210
Instruction Register
TDI
TDO
ID Code Register
· 31 30 29 · · · 2 1 0
Control Signals
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.04 4/2005
16/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology