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| GS8150V18AB Datasheet, PDF (14/25 Pages) GSI Technology – 1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM | |||
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Product Preview
GS8150V18/36AB-357/333/300/250
ZZ Timing
K
A
SS
SW
SWx
ZZ
DQn
KHKH
Read A1 Read A2
KHKL
KLKH
Deselect
Clock is a Don't care during Sleep ModeRead A1
Read A2
Read A3
tAVKH
tKHAX
A1
A2
tEVKH
tKHEX
A1
A2
A3
tWVKH
tKHWX
Begin ISB
ZZE
KHQX1
Q1
Q2
ZZR
KHQV
Q1
KHQX
Note:
K is not shown; assumes K tied to VREF or out of phase with K
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
Rev: 1.04 4/2005
14/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
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