GS8182T19 Datasheet, PDF (7/27 Pages) GSI Technology – 18Mb SigmaDDR-II+TM Burst of 2 SRAM

GS8182T19/37BD-435/400/375/333/300
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaDDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
V_SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance at mid-rail. The allowable range of RQ to guarantee impedance matching
continuously is between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is
affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply
voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each
impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver
is implemented with discrete binary weighted impedance steps.
Common I/O SigmaDDR-II+ B2 SRAM Truth Table
DQ
K_n
LD
R/W
A+0
A+1
Operation
↑
1
X
↑
0
0
↑
0
1
Note:
Q is controlled by K clocks if C clocks are not used.
Hi-Z
D@K_n+1
Q@K(n+2) for A+0
Hi-Z
D@K_n+1
Q@K(n+2 ) for
A+1
Deselect
Write
Read
Rev: 1.03a 11/2011
7/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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