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GS8182T19 Datasheet, PDF (1/27 Pages) GSI Technology – 18Mb SigmaDDR-II+TM Burst of 2 SRAM | |||
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GS8182T19/37BD-435/400/375/333/300
165-Bump BGA
Commercial Temp
Industrial Temp
18Mb SigmaDDR-II+TM
Burst of 2 SRAM
435 MHzâ300 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
⢠2.0 Clock Latency
⢠Simultaneous Read and Write SigmaDDR-II⢠Interface
⢠Common I/O bus
⢠JEDEC-standard pinout and package
⢠Double Data Rate interface
⢠Byte Write (x36 and x18) function
⢠Burst of 2 Read and Write
⢠1.8 V +100/â100 mV core power supply
⢠1.5 V or 1.8 V HSTL Interface
⢠Pipelined read operation with self-timed Late Write
⢠Fully coherent read and write pipelines
⢠ZQ pin for programmable output drive strength
⢠IEEE 1149.1 JTAG-compliant Boundary Scan
⢠165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
⢠RoHS-compliant 165-bump BGA package available
SigmaDDR-II⢠Family Overview
The GS8182T19/37BD are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 18,874,368-bit (18Mb)
SRAMs. The GS8182T19/37BD SigmaDDR-II SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8182T19/37BD SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaDDR-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore the address field of a
SigmaDDR-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 2M x 8 has a 1M
addressable index).
tKHKH
tKHQV
-435
2.3 ns
0.45 ns
Parameter Synopsis
-400
2.5 ns
0.45 ns
-375
2.67 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
Rev: 1.03a 11/2011
1/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2008, GSI Technology
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