GS8182D37BD-400 Datasheet, PDF (7/27 Pages) GSI Technology – 18Mb SigmaQuad-II+ Burst of 4 SRAM

GS8182D19/37BD-435/400/375/333/300
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Separate I/O SigmaQuad II+ B4 SRAM Truth Table
Previous
Operation
A
RW
Current
Operation
D
D
D
D
Q
Q
Q
Q
K↑
(t_n-1)
Deselect
K
K
K
↑↑↑
(t_n) (t_n) (t_n)
X
1
1
K↑
(t_n)
Deselect
K↑
(t_n+1)
K↑
(t_n+1½)
K↑
(t_n+2)
K↑
t(_n+2½)
K↑
(t_n+2)
K↑
t(_n+2½)
K↑
t(_n+3)
K↑
t(_n+3½)
X
X
—
—
Hi-Z
Hi-Z
—
—
Write
X
1
X
Deselect
D2
D3
—
—
Hi-Z
Hi-Z
—
—
Read
X
X
1
Deselect
X
X
—
—
Q2
Q3
—
—
Deselect
V
1
0
Write
D0
D1
D2
D3
Hi-Z
Hi-Z
—
—
Deselect
V
0
X
Read
X
X
—
—
Q0
Q1
Q2
Q3
Read
V
X
0
Write
D0
D1
D2
D3
Q2
Q3
—
—
Write
V
0
X
Read
D2
D3
—
—
Q0
Q1
Q2
Q3
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-
ceded by a Read command.
6. Users should not clock in metastable addresses.
Rev: 1.03a 11/2011
7/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2008, GSI Technology