GS8182D37BD-400 Datasheet, PDF (1/27 Pages) GSI Technology – 18Mb SigmaQuad-II+ Burst of 4 SRAM

165-Bump BGA
Commercial Temp
Industrial Temp
GS8182D19/37BD-435/400/375/333/300
18Mb SigmaQuad-II+
Burst of 4 SRAM
435 MHz–300 MHz
1.8 V V_DD
1.8 V and 1.5 V I/O
Features
• 2.0 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD)
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuad™ Family Overview
The GS8182D19/37D are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 18,874,368-bit (18Mb)
SRAMs. The GS8182D19/37D SigmaQuad SRAMs are just
one element in a family of low power, low voltage HSTL I/O
SRAMs designed to operate at the speeds needed to implement
economical high performance networking systems.
Clocking and Addressing Schemes
The GS8182D19/37D SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II B4 RAM is always two address pins
less than the advertised index depth (e.g., the 2M x 8 has a
512K addressable index).
tKHKH
tKHQV
-435
2.3 ns
0.45 ns
Parameter Synopsis
-400
2.5 ns
0.45 ns
-375
2.67 ns
0.45 ns
-333
3.3 ns
0.45 ns
-300
3.0 ns
0.45 ns
Rev: 1.03a 11/2011
1/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2008, GSI Technology