GS8182D37BD-400 Datasheet, PDF (15/27 Pages) GSI Technology – 18Mb SigmaQuad-II+ Burst of 4 SRAM

GS8182D19/37BD-435/400/375/333/300
AC Electrical Characteristics
Parameter
Symbol
Clock
K, K Clock Cycle Time
tKC Variable
K, K Clock High Pulse Width
K, K Clock Low Pulse Width
K to K High
K to K High
DLL Lock Time
K Static to DLL reset
Output Times
K, K Clock High to Data Output Valid
K, K Clock High to Data Output Hold
K, K Clock High to Echo Clock Valid
K, K Clock High to Echo Clock Hold
t_KHKH
t_KVar
t_KHKL
t_KLKH
t_KHKH
t_KHKH
t_KLock
t_KReset
t_KHQV
t_KHQX
t_KHCQV
t_KHCQX
-435
Min Max
2.3
8.4
—
0.2
0.4
—
0.4
—
1.00
—
1.00
—
2048
—
30
—
—
0.45
–0.45
—
—
0.45
–0.45
—
-400
Min Max
2.5
8.4
—
0.2
0.4
—
0.4
—
1.06
—
1.06
—
2048
—
30
—
—
0.45
–0.45
—
—
0.45
–0.45
—
-375
Min Max
-333
Min Max
-300
Min Max
2.67 8.4
3.0
8.4
3.3
8.4 ns
—
0.2
—
0.2
—
0.2 ns 4
0.4
—
0.4
—
0.4
—
ns
0.4
—
0.4
—
0.4
—
ns
1.13
—
1.28
—
1.4
—
ns
1.13
—
1.28
—
1.4
—
ns
2048 — 2048 — 2048 — cycle 6
30
—
30
—
30
—
ns
—
0.45
—
0.45
—
0.45 ns
–0.45 — –0.45 — –0.45 —
ns
—
0.45
—
0.45
—
0.45 ns
–0.45 — –0.45 — –0.45 —
ns
CQ, CQ High Output Valid
t_CQHQV
—
0.2
—
0.2
—
0.2
—
0.2
—
0.2 ns 7
CQ, CQ High Output Hold
t_CQHQX
–0.2
—
–0.2
—
–0.2
—
–0.2
—
–0.2
—
ns 7
CQ, CQ High to QLVD
t_QVLD
-0.2
-0.2
-0.2
-0.2
-0.2
CQ Phase Distortion
t_CQHCQH
0.8
—
0.86
—
0.88
—
1.03
—
1.15
—
ns
K Clock High to Data Output High-Z
t_KHQZ
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45 ns 5
K Clock High to Data Output Low-Z
Setup Times
t_KHQX1
–0.45
—
–0.45
—
–0.45 — –0.45 — –0.45 —
ns 5
Address Input Setup Time
Control Input Setup Time
(R, W)
Control Input Setup Time
(BWX) (NWX)
t_AVKH
0.4
—
0.4
—
0.4
—
0.4
—
0.4
—
ns 1
t_IVKH
0.4
—
0.4
—
0.4
—
0.4
—
0.4
—
ns 2
t_IVKH
0.28
—
0.28
—
0.28
—
0.28
—
0.28
—
ns 3
Data Input Setup Time
t_DVKH
0.28
—
0.28
—
0.28
—
0.28
—
0.28
—
ns
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W,
3. Control singles are BW0, BW1 and (BW2, BW3 for x36).
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus conten-
tion because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX
parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and tempera-
tures.
6. V_DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V_DD and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet
parameters reflect tester guard bands and test setup variations.
Rev: 1.03a 11/2011
15/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2008, GSI Technology