GS71024 Datasheet, PDF (7/13 Pages) GSI Technology – 64K x 24 1.5Mb Asynchronous SRAM

Address
CE1^(*1)
V/S
Read Cycle 2: WE = V_IH
t_RC
t_AA
t_AC
t_LZ
t_HZ
t_AV
OE
Data Out
t_OE
t_OLZ
High impedance
t_OHZ
Data valid
*1 CE1 represents both CE1 low and CE2 high.
GS71024T/U
Rev: 1.05 11/2004
7/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology