GS71024 Datasheet, PDF (1/13 Pages) GSI Technology – 64K x 24 1.5Mb Asynchronous SRAM

TQFP, FP-BGA
Commercial Temp
Industrial Temp
64K x 24
1.5Mb Asynchronous SRAM
GS71024T/U
8, 9, 10, 12, 15 ns
3.3 V V_DD
Center V_DD and V_SS
Features
• Fast access time: 8, 9, 10, 12, 15 ns
• CMOS low power operation: 190/170/160/130/110 mA at
minimum cycle time.
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40 to 85°C
• Package
T: 100-pin TQFP package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array
GT: Pb-Free 100-pin TQFP available
Description
The GS71024 is a high speed CMOS static RAM organized as
65,536 words by 24 bits. Static design eliminates the need for
external clocks or timing strobes. The GS71024 operates on a
single 3.3 V power supply, and all inputs and outputs are TTL-
compatible. The GS71024 is available in a 6 mm x 8 mm Fine
Pitch BGA package, as well as in a 100-pin TQFP package.
Fine Pitch BGA Bump Configuration
123456
A DQ A3 A2 A1 A0 DQ
B DQ DQ CE2 WE DQ DQ
C DQ DQ CE1 OE DQ DQ
D V_SS DQ A5 A4 DQ V_DD
E V_DD DQ A7 A6 DQ V_SS
F DQ DQ A9 A8 DQ DQ
G DQ DQ A11 A10 DQ DQ
H DQ A15 A14 A13 A12 DQ
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Pin Descriptions
Symbol
A0 to A15
X/Y
WE
CE1, CE2
V_DD
Description
Symbol
Address input
DQ1 to DQ24
Vector Input
V/S
Write enable input
OE
Chip enable input
—
+3.3 V power supply
V_SS
Block Diagram
Description
Data input/output
Address Multiplexer Control
Output enable input
—
Ground
A0
A14
A15
X/Y
0
1
Q
V/S
CE1
CE2
WE
OE
Address
Input
Control
Row
Decoder
Memory Array
1024 x 1536
Column
Decoder
I/O Buffer
DQ1
DQ24
Rev: 1.05 11/2004
1/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology