GS71024 Datasheet, PDF (6/13 Pages) GSI Technology – 64K x 24 1.5Mb Asynchronous SRAM

GS71024T/U
AC Characteristics
Read Cycle
Parameter
-8
-9
-10
-12
-15
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max
Read cycle time
t_RC
8 — 9 — 10 — 12 — 15 — ns
Address access time
t_AA
— 8 — 9 — 10 — 12 — 15 ns
Chip enable access time (CE1, CE2)
t_AC
— 8 — 9 — 10 — 12 — 15 ns
MUX control to output valid (V/S)
t_AV
— 8 — 9 — 10 — 12 — 15 ns
Output enable to output valid (OE)
t_OE
— 4 — 4.5 — 5 — 6 — 7 ns
Output hold from address change
t_OH
3 — 3 — 3 — 3 — 3 — ns
Output hold from MUX controls change
t_OH1
3 — 3 — 3 — 3 — 3 — ns
Chip enable to output in low Z (CE1, CE2)
t_LZ*
3 — 3 — 3 — 3 — 3 — ns
Output enable to output in low Z (OE)
t_OLZ*
0 — 0 — 0 — 0 — 0 — ns
Chip disable to output in High Z (CE1, CE2)
t_HZ*
— 4 — 4.5 — 5 — 6 — 7 ns
Output disable to output in High Z (OE)
t_OHZ* — 4 — 4.5 — 5 — 6 — 7 ns
* These parameters are sampled and are not 100% tested
Address
V/S
Data Out
Read Cycle 1: CE = OE = V_IL, WE = V_IH
t_RC
t_AA
t_OH
Previous Data
t_OH1
t_AV
Data valid
Rev: 1.05 11/2004
6/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology