GS816218BB-V Datasheet, PDF (6/31 Pages) GSI Technology – 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs

Preliminary
GS8162xxBB-xxxV
Mode Pin Functions
Mode Name
Pin Name State
Function
Burst Order Control
L
LBO
H
Linear Burst
Interleaved Burst
Output Register Control
L
FT
H or NC
Flow Through
Pipeline
Power Down Control
L or NC
ZZ
H
Active
Standby, I_DD = I_SB
Single/Dual Cycle Deselect Control
L
SCD
H or NC
Dual Cycle Deselect
Single Cycle Deselect
FLXDrive Output Impedance Control
L
ZQ
H or NC
High Drive (Low Impedance)
Low Drive (High Impedance)
Note:
There are pull-up devices on the ZQ, and SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and
the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.01a 6/2006
6/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology