GS816218BB-V Datasheet, PDF(4/31 Page) GSI Technology – 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs

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GS816218BB-V Datasheet, PDF (4/31 Pages) GSI Technology – 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs

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Preliminary

GS8162xxBB-xxxV

GS816218/36BB-xxxV BGA Pin Description

Symbol

A0, A1

A

DQA

DQB

DQC

DQD

BA, BB, BC, BD

NC

CK

BW

GW

E1

G

ADV

ADSP, ADSC

ZZ

FT

LBO

ZQ

SCD

TMS

TDI

TDO

TCK

VDD

VSS

VDDQ

Type

I

I

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

I/O

Data Input and Output pins

I

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

â

No Connect

I

Clock Input Signal; active high

I

Byte WriteâWrites all enabled bytes; active low

I

Global Write EnableâWrites all bytes; active low

I

Chip Enable; active low

I

Output Enable; active low

I

Burst address counter advance enable; active low

I

Address Strobe (Processor, Cache Controller); active low

I

Sleep mode control; active high

I

Flow Through or Pipeline mode; active low

I

Linear Burst Order mode; active low

I

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

I

Single Cycle Deselect/Dual Cyle Deselect Mode Control

I

Scan Test Mode Select

I

Scan Test Data In

O

Scan Test Data Out

I

Scan Test Clock

I

Core power supply

I

I/O and Core Ground

I

Output driver power supply

Rev: 1.01a 6/2006

4/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Â© 2004, GSI Technology

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