GS74104TP Datasheet, PDF (6/12 Pages) GSI Technology – 1M x 4 4Mb Asynchronous SRAM

AC Characteristics
GS74104TP/J
Read Cycle
Parameter
Read cycle time
Address access time
Chip enable access time (CE)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
Output enable to output in low Z (OE)
Chip disable to output in High Z (CE)
Output disable to output in High Z (OE)
-8
-10
-12
-15
Symbol
Unit
Min Max Min Max Min Max Min Max
tRC
8
— 10 — 12
— 15 —
ns
tAA
—
8
—
10 — 12 — 15
ns
tAC
—
8
—
10 — 12 — 15
ns
tOE
— 3.5 —
4
—
5
—
6
ns
tOH
3
—
3
—
3
—
3
—
ns
tLZ^*
3
—
3
—
3
—
3
—
ns
tOLZ^*
0
—
0
—
0
—
0
---
ns
tHZ^*
—
4
—
5
—
6
—
7
ns
tOHZ^*
— 3.5 —
4
—
5
—
6
ns
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = V_IL, WE = V_IH
Address
Data Out
tOH
Previous Data
tRC
tAA
Data valid
Rev: 1.07 1/2001
6/12
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.