GS73024AB Datasheet, PDF (6/12 Pages) GSI Technology – Asynchronous SRAM

GS73024AB
AC Characteristics
Read Cycle
Parameter
-8
-10
-12
Symbol
Unit
Min Max Min Max Min Max
Read cycle time
t_RC
8
—
10
—
12
—
ns
Address access time
t_AA
—
8
—
10
—
12
ns
Chip enable access time (CE)
t_AC
—
8
—
10
—
12
ns
MUX control to output valid (V/S)
t_AV
—
8
—
10
—
12
ns
Output enable to output valid (OE)
t_OE
—
4
—
5
—
6
ns
Output hold from address change
t_OH
3
—
3
—
3
—
ns
Output hold from MUX controls change
t_OH1
3
—
3
—
3
—
ns
Chip enable to output in low Z (CE)
t_LZ*
3
—
3
—
3
—
ns
Output enable to output in low Z (OE)
t_OLZ*
0
—
0
—
0
—
ns
Chip disable to output in High Z (CE)
t_HZ*
—
4
—
5
—
6
ns
Output disable to output in High Z (OE)
t_OHZ*
—
4
—
5
—
6
ns
* These parameters are sampled and are not 100% tested
Read Cycle 1: CE = OE = V_IL, WE = V_IH
Address
Data Out
t_OH
Previous Data
t_RC
t_AA
Data valid
Rev: 1.03 12/2005
6/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology