GS8321ZV18 Datasheet, PDF (5/31 Pages) GSI Technology – 36Mb Pipelined and Flow Through Synchronous NBT SRAM

GS8321ZV18/32/36E-250/225/200/166/150/133
GS8321ZV18/32/36E 165-Bump BGA Pin Description
Symbol
A0, A1
An
DQA
DQB
DQC
DQD
BA, BB, BC, BD
NC
CK
CKE
W
E1
E3
E2
FT
G
ADV
ZZ
LBO
TMS
TDI
TDO
TCK
MCH
V_DD
V_SS
V_DDQ
Type
I
I
I/O
I
—
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
—
I
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
Clock Input Signal; active high
Clock Enable; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; active low
Chip Enable; active high
Flow Through / Pipeline Mode Control
Output Enable; active low
Burst address counter advance enable; active high
Sleep mode control; active high
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Must Connect High
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.03 11/2004
5/31
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.