GS8321ZV18 Datasheet, PDF (16/31 Pages) GSI Technology – 36Mb Pipelined and Flow Through Synchronous NBT SRAM

GS8321ZV18/32/36E-250/225/200/166/150/133
AC Test Conditions
Parameter
Conditions
Input high level
V_DD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V_DD/2
Output reference level
V_DDQ/2
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics
Parameter
Input Leakage Current
(except mode pins)
ZZ Input Current
FT, SCD, and ZQ Input Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Output Load 1
DQ
50Ω
30pF^*
V_DDQ/2
* Distributed Test Jig Capacitance
Symbol
I_IL
I_IN1
I_IN2
I_OL
V_OH1
V_OL1
Test Conditions
V_IN = 0 to V_DD
V_DD ≥ V_IN ≥ V_IH
0 V ≤ V_IN ≤ V_IH
V_DD ≥ V_IN ≥ V_IL
0 V ≤ V_IN ≤ V_IL
Output Disable, V_OUT = 0 to V_DD
I_OH = –4 mA, V_DDQ = 1.6 V
I_OL = 4 mA, V_DD = 1.6 V
Min
Max
–1 uA
1 uA
–1 uA
–1 uA
–100 uA
–1 uA
–1 uA
V_DDQ – 0.4 V
—
1 uA
100 uA
1 uA
1 uA
1 uA
—
0.4 V
Rev: 1.03 11/2004
16/31
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.