GS8321ZV18 Datasheet, PDF (11/31 Pages) GSI Technology – 36Mb Pipelined and Flow Through Synchronous NBT SRAM

GS8321ZV18/32/36E-250/225/200/166/150/133
Flow Through Mode Data I/O State Diagram
BW
R
High Z
(Data In)
D
WR
High Z
B
D
RB
Data Out
W _{(Q Valid)}
D
Key
Input Command Code
ƒ _Transition
Current State (n)
Next State (n+1)
n
n+1
Clock (CK)
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
n+2
n+3
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow through Read Write Control State Diagram
Rev: 1.03 11/2004
11/31
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.