GS8162Z72C Datasheet, PDF (4/31 Pages) GSI Technology – 18Mb Pipelined and Flow Through Synchronous NBT SRAM

GS8162Z72C
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Byte Write Truth Table
Function
GW
BW
BA
BB
BC
BD
BE
BF
BG
BH Notes
Read
H
H
X
X
X
X
X
X
X
X
1
Read
H
L
H
H
H
H
H
H
H
H
1
Write byte A
H
L
L
H
H
H
L
H
H
H
2, 3
Write byte B
H
L
H
L
H
H
H
L
H
H
2, 3
Write byte C
H
L
H
H
L
H
H
H
L
H
2, 3, 4
Write byte D
H
L
H
H
H
L
H
H
H
L
2, 3, 4
Write byte E
H
L
H
H
H
H
L
H
H
H
2, 3, 4
Write byte F
H
L
H
H
H
H
H
L
H
H
2, 3, 4
Write byte G
H
L
H
H
H
H
H
H
L
H
2, 3, 4
Write byte H
H
L
H
H
H
H
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, BD, BE, BF, BG, and/or BH may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “E”, “F”, “G” and “H” are only available on the x72 version.
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Rev: 2.22 11/2005
4/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology