GS8162Z72C Datasheet, PDF (1/31 Pages) GSI Technology – 18Mb Pipelined and Flow Through Synchronous NBT SRAM

GS8162Z72C
209-bump BGA
Commercial Temp
Industrial Temp
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
200 MHz–133 MHz
2.5 V or 3.3 V V_DD
2.5 V or 3.3 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 209-Bump BGA package
Functional Description
The GS8162Z72C is an 18Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8162Z72C may be configured by the user to operate in
Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising edge triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge-triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS8162Z72C is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 209-bump BGA package.
Pipeline
3-1-1-1
3.3 V
2.5 V
Flow Through
2-1-1-1
3.3 V
2.5 V
Parameter Synopsis
t_KQ
tCycle
Curr (x72)
Curr (x72)
t_KQ
tCycle
Curr (x72)
Curr (x72)
-200 -166 -150 -133 Unit
3.0
3.4
3.8
4.0
ns
5.0
6.0
6.7
7.5
ns
350
300
270
245
mA
335
290
260
235
mA
6.5
7.0
7.5
8.5
ns
6.5
7.0
7.5
8.5
ns
225
115
210
185
mA
225
115
210
185
mA
Rev: 2.22 11/2005
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology