GS8162Z72C Datasheet, PDF (3/31 Pages) GSI Technology – 18Mb Pipelined and Flow Through Synchronous NBT SRAM

GS8162Z72 BGA Pin Description
Symbol
A0, A1
An
DQA
DQB
DQC
DQD
DQE
DQF
DQG
DQH
BA, BB, BC,BD, BE, BF,
BG,BH
NC
CK
W
E1, E3
E2
G
ZZ
FT
LBO
MCH
MCL
PE
ADV
Type
I
I
I/O
I
—
I
I
I
I
I
I
I
I
I
I
I
ZQ
I
TMS
I
TDI
I
TDO
O
TCK
I
V_DD
I
V_SS
I
V_DDQ
I
GS8162Z72C
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD, DQE,
DQF, DQG, DQH I/Os; active low
No Connect
Clock Input Signal; active high
Write Enable. Writes all enabled bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Must Connect High
Must Connect Low
Parity Bit Enable; active low (High = x64 Mode, Low = x72 Mode)
Burst Address Counter Advance Enable; active high
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 2.22 11/2005
3/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology