GS8182Q18BD-300M Datasheet, PDF (1/35 Pages) GSI Technology – 18Mb SigmaQuad-IITM Burst of 2 SRAM

GS8182Q08/09/18/36BD-300M
165-Bump BGA
Military Temp
18Mb SigmaQuad-II^TM
Burst of 2 SRAM
300 MHz
1.8 V V_DD
1.8 V and 1.5 V I/O
Features
• Military Temperature Range
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with 36Mb, 72Mb, and 144Mb devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
SigmaQuad™ Family Overview
The GS8182Q08/09/18/36BD-300M are built in compliance
with the SigmaQuad-II SRAM pinout standard for Separate
I/O synchronous SRAMs. They are 18,874,368-bit (18Mb)
SRAMs. The GS8182Q08/09/18/36BD-300M SigmaQuad
SRAMs are just one element in a family of low power, low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The GS8182Q08/09/18/36BD-300M SigmaQuad-II SRAMs
are synchronous devices. They employ two input register
clock inputs, K and K. K and K are independent single-ended
clock inputs, not differential inputs to a single differential
clock input buffer. The device also allows the user to
manipulate the output register clock inputs quasi independently
with the C and C clock inputs. C and C are also independent
single-ended clock inputs, not differential inputs. If the C
clocks are tied high, the K clocks are routed internally to fire
the output registers instead.
Each internal read and write operation in a SigmaQuad-II B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore the address field of a
SigmaQuad-II B2 RAM is always one address pin less than the
advertised index depth (e.g., the 2M x 8 has a 1M addressable
index).
Parameter Synopsis
tKHKH
tKHQV
-300M
3.3 ns
0.45 ns
Rev: 1.00a 11/2011
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology