GS2970A Datasheet, PDF (87/150 Pages) Gennum Corporation – Integrated audio clock generator

When a one-bit error is detected in a bit array of the ECC protected region of the audio
data packet with audio group DID set in IDA[1:0], the ECCA_ERROR flag is set HIGH.
When a one-bit error is detected in the ECC protected region of the audio data packet
with audio group DID set in IDB[1:0], the ECCB_ERROR flag is set HIGH.
Figure 4-43 shows examples of error correction and detection. Up to 8 bits in error can
be corrected, providing each bit error is in a different bit array (shown below). When
there are two or more bits in error in the same 24-bit array, the errors are detected, but
not corrected.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
24-bit array
ADF ADF ADF DID DBN DC CLK CLK CH1 CH1 CH1 CH1 CH2 CH2 CH2 CH2 CH3 CH3 CH3 CH3 CH4 CH4 CH4 CH4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Errors corrected
ADF ADF ADF DID DBN DC CLK CLK CH1 CH1 CH1 CH1 CH2 CH2 CH2 CH2 CH3 CH3 CH3 CH3 CH4 CH4 CH4 CH4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Errors detected but not corrected
Figure 4-43:ECC 24-bit Array and Examples
4.19.3 Audio Processing
4.19.3.1 Audio Clock Generation
For SD and HD/3G audio, a single set of audio frequencies is generated for all audio
channels, using a Direct Digital Period Synthesizer (DDPS) to minimize jitter.
• For Mapping structure one signals (1080p 50, 59.94 or 60), the pixel clock is
148.5(/M) MHz, and the phase data are based on this rate. An Audio Master Clock
(AMCLK) is also generated. The frequency is selectable via the host interface as:
Š fs x 128
Š fs x 256
Š fs x 512
In SD mode, audio clocks are derived from the PCLK.
In HD/3G modes, the input control for the DDPS is derived from the two embedded
audio clock phase words in the audio data packet corresponding to Group A. The audio
clock phase information used is taken from the first embedded audio packet in the
HANC space. With no embedded audio present, the device will not generate ACLK or
WCLK. The IGNORE_PHASE bit should be asserted in this case to ensure the proper
AMCLK frequency is generated.
GS2970A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54244 - 2
September 2012
87 of 150