GS2970A Datasheet, PDF (118/150 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-28:SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name
407h
SD_AUDIO_ERR
OR_MASK
EN_ADPG4_DET
EN_ADPG3_DET
EN_ADPG2_DET
EN_ADPG1_DET
408h
CFG_OUTPUT ASWLD
ASWLC
ASWLB
ASWLA
AMD
AMC
AMB
AMA
Bit Description
3
2
1
0
15-14
13-12
11-10
9-8
7-6
5-4
3-2
1-0
Asserts interrupt when the
ADPG4_DET flag is set.
Asserts interrupt when the
ADPG3_DET flag is set.
Asserts interrupt when the
ADPG2_DET flag is set.
Asserts interrupt when the
ADPG1_DET flag is set.
Output channels 7 and 8 word
length.
00: 24 bits
01: 20 bits
10: 16 bits
11: Automatic 20-bit or 24-bit
Output channels 5 and 6 word
length. (See above for decoding)
Output channels 3 and 4 word
length. (See above for decoding)
Output channels 1 and 2 word
length. (See above for decoding)
Output channels 7 and 8 format
selector.
00: AES/EBU audio output
01: Serial audio output: Left
justified; MSB first
10: Serial audio output: Right
justified; MSB first
11: I²S serial audio output
Output channels 5 and 6 format
selector. (See above for decoding).
Output channels 3 and 4 format
selector. (See above for decoding).
Output channels 1 and 2 format
selector. (See above for decoding).
R/W
R/W
Default
0
R/W
0
R/W
0
R/W
0
R/W
3
R/W
3
R/W
3
R/W
3
R/W
3
R/W
3
R/W
3
R/W
3
GS2970A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54244 - 2
September 2012
118 of 150